1. Field of the Invention
The present invention relates to an analog-to-digital converter. In particular, the invention relates to analog-to-digital conversion technologies of cyclic type.
2. Description of the Related Art
(First Related Art)
Recently, cellular phones have incorporated a variety of additional functions such as an image capturing function, an image reproducing function, a moving image capturing function, and a moving image reproducing function. Reduced size and reduced power consumption are thus increasingly required of analog-to-digital converters (hereinafter, referred to as “AD converters”). One of the known forms of such AD converters is a cyclic AD converter which has a cyclic configuration (for example, see Japanese Patent Laid-Open Publication No. Hei 11-145830). FIG. 13 shows the configuration of a conventional cyclic AD converter. In this AD converter 150, an analog signal Vin input through a first switch 152 is sampled by a first amplifier circuit 156, and converted into a 1-bit digital value by an AD conversion circuit 158. The digital value is converted into an analog value by a DA conversion circuit 160, and subtracted from the input analog signal Vin by a subtractor circuit 162. The output of the subtractor circuit 162 is amplified by a second amplifier circuit 164, and fed back to the first amplifier circuit 156 through a second switch 154. This feedback-based cyclic processing is repeated 12 times to obtain 12 bits of digital value.
(Second Related Art)
There is known another form of the cyclic AD converter which has a cyclic configuration (for example, see Japanese Patent Laid-Open Publication No. Hei 4-26229).
FIG. 26 shows an example of the conventional cyclic AD converter. In this AD converter, an analog signal Vin input through a first switch SW101 is sampled and held by a sample-and-hold circuit 1011 as an analog signal equivalent to the input signal, and is converted into a digital value by an AD conversion circuit 1012. Initially, the top four bits are extracted. The digital value converted by the AD conversion circuit is converted into an analog value by a DA conversion circuit 1013. A subtractor 1014 subtracts the analog signal input from the DA conversion circuit 1013 from the input analog signal Vin that is sampled and held in the sample-and-hold circuit 1011. The output analog signal of the subtractor circuit 1014 is amplified by a second amplifier circuit 1015. Incidentally, the subtractor circuit 1014 and the second amplifier circuit may be a subtracting amplifier circuit 1016 of integral type. The analog signal amplified is fed back to the sample-and-hold circuit 1011 and the AD conversion circuit 1012 through a second switch SW102. In order to extract three bits at the second and subsequent cycles, the second amplifier circuit 1015 amplifies the input signal by eight. This cyclic processing is repeated to obtain a 13-bit digital value.
(First Problem)
The cyclic AD converter described in Japanese Patent Laid-Open Publication No. Hei 11-145830 is advantageous in suppressing the circuit area since it has a smaller number of elements as compared to multistage pipelined AD converters. For the sake of the reduced circuit area, however, the same circuits must be used repeatedly under the same condition throughout all the stages of the cyclic processing. Thus, specifications of the individual circuits included in the cyclic AD converter must be designed in view of the conversion of upper bits where particularly high conversion processing speed and conversion accuracy are required. This means that the conversion processing speed and conversion accuracy to be secured can sometimes be excessive to the entire process of the cyclic processing. Besides, securing excessive conversion processing speed and conversion accuracy throughout all the stages of the cyclic processing tends to increase the power consumption.
(Second Problem)
The cyclic AD converter described in Japanese Patent Laid-Open Publication No. Hei 4-26229 extracts upper bits before the subtraction of the corresponding analog signal. Thus, the analog signal resulting from the subtraction must be amplified according to the number of bits for the AD conversion circuit in the subsequent stages to extract.
Nevertheless, amplifier circuits have a limit of the gain bandwidth product (GB product). More specifically, obtaining higher gains lowers the operating frequencies of the amplifier circuits, which can make high speed operation difficult. Then, if the AD conversion circuit of cyclic type can change its signal range necessary for the conversion at the second and subsequent cycles by using a substitute technique other than the amplification of the input analog signal, it is possible to ease the limitation of the amplifier circuit and enhance the design flexibility of the entire AD converter.